The field of this invention relates to radio-frequency digital-to-amplitude converter(s) (RF-DAC(s). The invention is applicable to, but not limited to, radio-frequency digital-to-amplitude converter(s) (RF-DAC(s)) employing pulse width modulation.
One of the most important radio frequency (RF) architectural/circuit changes in the last decade has been the digitization of RF transceivers, such that digital functionality in the RF domain is now a key aspect for most wireless applications. Thus, for low-cost and low-power wireless devices, system-on-chip (SoC) integration of RF circuits with digital circuits has proven to be popular. One example of this is in digital RF transmitters, which now comprise digital application specific integrated circuit (ASIC) cells and one or more radio-frequency digital-to-amplitude converter(s) (RF-DAC(s)).
Some recent publications on RF transmitters have shown that employing an RF-DAC can make RF SoC implementation easier, for example R. Staszewski, et al. “All-digital PLL and transmitter for mobile phones”, published in IEEE J. Solid-State Circuits, vol. 40, no. 12, pp 2469-2482, December 2005 [1], J. Mehta, et al. “A 0.8 mm2 11-digital SAW-less polar transmitter in 65 nm EDGE SoC”, published in Proc. of IEEE Solid-State Circuits Conf, pp 58-59, December 2010 [2], A. Jerng, et al. “A wideband sigma-delta digital RF modulator for high data rate transmitters”, published in IEEE Solid-State Circuits, vol. 42, no. 8, pp 1710-1722, Aug. 2007 [3], P. Eloranta, et al. “A multimode Transmitter in 0.13 m Using Direct-Digital RF Modulator”, published in IEEE J. Solid-State Circuits, vol. 42, no. 12, pp 2774-2784, December 2007 [1]. Among them, the commercial single-chip GSM/EDGE transceiver in [1, 2] is unique in that it uses a simple array of unit-weighted transistor switches to control the output RF amplitude, which operates as near class-E power amplifier, instead of using a traditional current-source based DAC structure.
Concurrently to the digitization of RF transceivers, the RF performance requirements in wireless applications have been increasing, for example to support surface acoustic wave (SAW) filter removal, multi-mode operation, multi-band operation, to meet coexistence requirements, etc. It is known that RF-DAC's need to achieve extremely-high resolution performance levels, which have so far been difficult to achieve in a practical, cost-effective manner. The traditional means of amplitude resolution in RF-DACs is limited due to device mismatches, where the typical method of ΣΔ dithering through noise shaping does not work well in SAW-less and multi-radio systems.
FIG. 1 illustrates the polar transmitter 100 introduced in [1, 2]. The I/Q baseband data is converted into digital amplitude modulation (AM) and phase/frequency modulation (PM/FM) signals. The frequency signal is fed into the DCO-based NF-bit digital-to-frequency converter (DFC), which generates a digital phase-modulated RF carrier by means of an all-digital PLL (ADPLL). The amplitude signal drives the NA-bit digital-to-RF-amplitude converter (DRAC), which includes a digitally-controlled power amplifier (DPA).
The DPA controls the envelope of the phase-modulated RF carrier, hence it is considered an RF-DAC. The DPA is different from the traditional RF-DACs in [3] or [4], because it does not use current sources. Therefore, the DPA is more compatible with low-voltage and low-cost digital CMOS processes than the traditional RF-DAC. Lack of current sources in the DPA results in somewhat compressed transfer function, but the look-up-table (LUT) for AM-AM and AM-PM predistortion in the amplitude signal path shown in FIG. 1 linearizes the DPA transfer function.
Referring now to FIG. 1, a known polar transmitter based on a DCO and DPA circuits from [2] is illustrated. For simplicity purposes, the all-digital PLL around the DCO is not shown. References [1, 2] have proved that the architecture in FIG. 1 is feasible for SoC meeting all GSM and EDGE specifications. However, the resolution of the amplitude modulation path is limited by lithography and RF mismatches (i.e., both amplitude and phase/delay) of the unit switching devices in the DPA, and, consequently, the polar transmitter has little margin in the far-out (i.e., the associated RX band) noise limit of the SAW-less operation for EDGE.
The amplitude resolution could be improved by ΣΔ dithering of the unit transistor switches [1, 2]. However, the quantization noise is pushed to higher frequencies where emission requirements might sometimes be difficult to satisfy, especially when considering radio coexistence in a wireless connectivity (e.g., Bluetooth, WLAN) or in a multi-core RF-SoC environment.
Referring now to FIG. 2, a known concept 200 of achieving amplitude modulation (AM) through pulse width modulation (PWM) is illustrated. As shown, in the graphical waveform, the RF output amplitude is “proportional” to the duty cycle of a power amplifier input (PA_IN) signal. A duty cycle of the AM signal is controlled through precise delay.
The output amplitude of a PWM signal at the frequency of interest, however, is incorrect if the pulsewidth is chosen in a straightforward way, such that the DC amplitude of the PWM signal is correct, as illustrated in S. E. Meninger and M. H. Perrott, titled “A fractional-N synthesizer architecture utilising a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise” published in IEEE Trans. Circuits Systems, vol. 50, issue 11, pp. 839-849, November 2003[7], which is incorporated herein by reference and S. E. Meninger and M. H. Perrott, titled “An RF Pulse Width Modulator for switch mode power amplification of varying envelope signals” published in Proc. Silicon Monolithic Integrated Circuits in RF System Top meeting, pp. 277-280, January 2007 [8], which is incorporated herein by reference. This is in contrast with the normal up-conversion operation of the DPA, which acts as a mixer. As a result, this inaccurate RF output level at the carrier frequency turns out to limit the resolution improvement.
Thus, a need exists for an improved amplitude resolution of an RF-DAC and method therefor.